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Table of Contents

Hardware Acceleration

FortiGate 600E and 601E fast path architecture

The FortiGate 600E and 601E models feature the following front panel interfaces:

  • Two 10/100/1000BASE-T Copper (HA and MGMT, not connected to the NP6 processors)
  • Eight 10/100/1000BASE-T Copper (1 to 8)
  • Eight 1 GigE SFP (9 - 12, S1, S2, VW1, VW2) (S1 and S2 are configured as sniffer interfaces, VW1 and VW2 are configured as virtual wire interfaces)
  • Two 10 GigE SFP+ (X1 and X2) (cannot be configured to be SFP interfaces)

The following diagram also shows the QSGMII and XAUI port connections between the NP6 processor and the front panel interfaces.

The FortiGate 600E and 601E each include one NP6 processor. All supported traffic passing between any two data interfaces can be offloaded by the NP6 processor. Data traffic to be processed by the CPU takes a dedicated data path through the NP6 processor to the CPU.

The MGMT interface is not connected to the NP6 processor. Management traffic passes to the CPU over a dedicated management path that is separate from the data path. The HA interface is also not connected to the NP6 processors. To help provide better HA stability and resiliency, HA traffic uses a dedicated physical control path that provides HA control traffic separation from data traffic processing. The separation of management and HA traffic from data traffic keeps management and HA traffic from affecting the stability and performance of data traffic processing.

You can use the following get command to display the FortiGate 600E or 601E NP6 configuration. You can also use the diagnose npu np6 port-list command to display this information.

get hardware npu np6 port-list 
Chip   XAUI Ports        Max  Cross-chip 
                        Speed offloading 
------ ---- -------     ----- ---------- 
np6_0   0   x1           10G  Yes 
        1   port1        1G   Yes 
        1   port2        1G   Yes 
        1   port3        1G   Yes 
        1   port4        1G   Yes 
        1   port5        1G   Yes 
        1   port6        1G   Yes 
        1   port7        1G   Yes 
        1   port8        1G   Yes 
        1   port9        1G   Yes 
        1   port10       1G   Yes 
        1   port11       1G   Yes 
        1   port12       1G   Yes 
        1   s1           1G   Yes
        1   s2           1G   Yes 
        1   vw1          1G   Yes 
        1   vw2          1G   Yes 
        2   x2           10G  Yes 
        3 
------ ---- ------- ----- ----------

FortiGate 600E and 601E fast path architecture

The FortiGate 600E and 601E models feature the following front panel interfaces:

  • Two 10/100/1000BASE-T Copper (HA and MGMT, not connected to the NP6 processors)
  • Eight 10/100/1000BASE-T Copper (1 to 8)
  • Eight 1 GigE SFP (9 - 12, S1, S2, VW1, VW2) (S1 and S2 are configured as sniffer interfaces, VW1 and VW2 are configured as virtual wire interfaces)
  • Two 10 GigE SFP+ (X1 and X2) (cannot be configured to be SFP interfaces)

The following diagram also shows the QSGMII and XAUI port connections between the NP6 processor and the front panel interfaces.

The FortiGate 600E and 601E each include one NP6 processor. All supported traffic passing between any two data interfaces can be offloaded by the NP6 processor. Data traffic to be processed by the CPU takes a dedicated data path through the NP6 processor to the CPU.

The MGMT interface is not connected to the NP6 processor. Management traffic passes to the CPU over a dedicated management path that is separate from the data path. The HA interface is also not connected to the NP6 processors. To help provide better HA stability and resiliency, HA traffic uses a dedicated physical control path that provides HA control traffic separation from data traffic processing. The separation of management and HA traffic from data traffic keeps management and HA traffic from affecting the stability and performance of data traffic processing.

You can use the following get command to display the FortiGate 600E or 601E NP6 configuration. You can also use the diagnose npu np6 port-list command to display this information.

get hardware npu np6 port-list 
Chip   XAUI Ports        Max  Cross-chip 
                        Speed offloading 
------ ---- -------     ----- ---------- 
np6_0   0   x1           10G  Yes 
        1   port1        1G   Yes 
        1   port2        1G   Yes 
        1   port3        1G   Yes 
        1   port4        1G   Yes 
        1   port5        1G   Yes 
        1   port6        1G   Yes 
        1   port7        1G   Yes 
        1   port8        1G   Yes 
        1   port9        1G   Yes 
        1   port10       1G   Yes 
        1   port11       1G   Yes 
        1   port12       1G   Yes 
        1   s1           1G   Yes
        1   s2           1G   Yes 
        1   vw1          1G   Yes 
        1   vw2          1G   Yes 
        2   x2           10G  Yes 
        3 
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