NP7 performance optimized over KR links
The NP7 processor has a bandwidth capacity of 200 Gigabits consisting of two 100 GbE KR links numbered 0 and 1 that operate as a LAG. In most FortiGate NP7 architectures, if all of the FortiGate front panel data interfaces are operating at their maximum bandwidth, the NP7 processors would not be able to offload all of the traffic; the NP7 processors are oversubscribed. Usually though, interfaces don’t operate at maximum bandwidth.
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KR is the hardware technology employed by the 100G physical interfaces of the NP7 processor. The K indicates the interface is a 100G electrical (and not optical fiber) interface. R represents the physical coding sublayer (PCS) used by the interface. NP7 processor KR interfaces use 64B/66B scrambled encoding. For more information see the following Wikipedia articles: |
NP7 architectures include an internal switch fabric (ISF) that distributes traffic from front panel data interfaces to the interfaces of the NP7 processor LAG if the FortiGate has one NP7 processor, or LAGs if the FortiGate has multiple NP7 processors.
For FortiGates with model number 1000 or higher, you can use the following command to configure NPU port mapping to control how traffic is distributed to the NP7 processor LAGs and optionally to individual NP7 processor interfaces.
config system npu
config port-npu-map
edit <interface-name>
set npu-group-index <index>
end
You can refer to individual NP7 architectures in FortiGate NP7 architectures, starting with the FortiGate 1000F and 1001F fast path architecture for details about configuring NPU port mapping for individual FortiGate models.