DPDK CPU settings

On the FortiGate-VM, a DPDK engine is attached to an IPS engine, which shares the same process and is mapped to a CPU. A processing pipeline of four stages handles a packet from RX to TX:

1. DPDK RX
2. vNP
3. IPS
4. DPDK TX

You can freely determine the CPUs enabled for each pipeline stage by running the following commands:

config dpdk cpus

set [X] [Y]

end

Here X is one of the pipeline stages: rx-cpus, vnp-cpus, ips-cpus, and tx-cpus.

Y is a string expression of CPU IDs, which contains comma-delimited individual CPU IDs or ranges of CPU IDs separated by a dash.

The example enables CPUs 0, 2, 4, 6, 7, 8, 9. 10, and 15 to run the vNP pipeline stage:

set vnp-cpus 0,2,4,6-10,15

In FortiOS 7.6, Y can also be a special token string all, which means to use all available CPUs to run that pipeline stage. The system automatically determines the number of available CPUs. all is the default value of each pipeline stage's CPU setting.

The example uses all available CPUs to run the IPS pipeline stage:

set ips-cpus all

You must enable at least one CPU for each pipeline stage. Otherwise, DPDK early initialization fails.