FortiGate-5001E and 5001E1 fast path architecture

The FortiGate-5001E and 5001E1 features two NP6 processors and an integrated switch fabric. The integrated switch fabric allows you to configure aggregate interfaces between interfaces connected to different NP6s and supports offloading between for traffic entering and exiting from any interfaces.

The NP6s are connected to network interfaces as follows:

NP6_0 is connected to port1, port3, fabric1, and base1.
NP6_1 is connected to port2, port4, fabric2, and base2.

The following diagram also shows the XAUI port connections between the NP6 processors and the front panel interfaces and the integrated switch fabric.

NP6 default interface mapping

You can use the following get command to display the FortiGate-5001E NP6 configuration. The command output shows two NP6s named NP6_0 and NP6_1. The output also shows the interfaces (ports) connected to each NP6. You can also use the diagnose npu np6 port-list command to display this information.

get hardware npu np6 port-list
Chip   XAUI Ports            Max   Cross-chip 
                             Speed offloading 
------ ---- -------          ----- ---------- 

np6_0  0    port3            10G   Yes        
       1    
       2    base1            1G    Yes        
       3    
       0-3  port1            40G   Yes        
       0-3  fabric1          40G   Yes        
       0-3  fabric3          40G   Yes        
       0-3  fabric5          40G   Yes        
------ ---- -------          ----- ---------- 
np6_1  0    
       1    port4            10G   Yes        
       2    
       3    base2            1G    Yes        
       0-3  port2            40G   Yes        
       0-3  fabric2          40G   Yes        
       0-3  fabric4          40G   Yes        
------ ---- -------          ----- ----------

NP6 interface mapping with split ports

If you use the following CLI command to split port1:

config system global

set split-port port1

end

The new split ports (port1/1 to port 1/4) are mapped to the same NP6 as the port1 interface:

diagnose npu np6 port-list 
Chip   XAUI Ports            Max   Cross-chip 
                             Speed offloading 
------ ---- -------          ----- ---------- 
np6_0  0    port3            10G   Yes        
       0    port1/1          10G   Yes        
       1    port1/2          10G   Yes        
       2    base1            1G    Yes        
       2    port1/3          10G   Yes        
       3    port1/4          10G   Yes        
       0-3  fabric1          40G   Yes        
       0-3  fabric3          40G   Yes        
       0-3  fabric5          40G   Yes        
------ ---- -------          ----- ---------- 
np6_1  0    
       1    port4            10G   Yes        
       2    
       3    base2            1G    Yes        
       0-3  port2            40G   Yes        
       0-3  fabric2          40G   Yes        
       0-3  fabric4          40G   Yes        
------ ---- -------          ----- ----------

FortiGate-5001E and 5001E1 fast path architecture

The NP6s are connected to network interfaces as follows:

NP6_0 is connected to port1, port3, fabric1, and base1.

NP6_1 is connected to port2, port4, fabric2, and base2.

The following diagram also shows the XAUI port connections between the NP6 processors and the front panel interfaces and the integrated switch fabric.

NP6 default interface mapping

get hardware npu np6 port-list Chip XAUI Ports Max Cross-chip Speed offloading ------ ---- ------- ----- ---------- np6_0 0 port3 10G Yes 1 2 base1 1G Yes 3 0-3 port1 40G Yes 0-3 fabric1 40G Yes 0-3 fabric3 40G Yes 0-3 fabric5 40G Yes ------ ---- ------- ----- ---------- np6_1 0 1 port4 10G Yes 2 3 base2 1G Yes 0-3 port2 40G Yes 0-3 fabric2 40G Yes 0-3 fabric4 40G Yes ------ ---- ------- ----- ----------

NP6 interface mapping with split ports

If you use the following CLI command to split port1:

config system global

set split-port port1

end

The new split ports (port1/1 to port 1/4) are mapped to the same NP6 as the port1 interface:

diagnose npu np6 port-list Chip XAUI Ports Max Cross-chip Speed offloading ------ ---- ------- ----- ---------- np6_0 0 port3 10G Yes 0 port1/1 10G Yes 1 port1/2 10G Yes 2 base1 1G Yes 2 port1/3 10G Yes 3 port1/4 10G Yes 0-3 fabric1 40G Yes 0-3 fabric3 40G Yes 0-3 fabric5 40G Yes ------ ---- ------- ----- ---------- np6_1 0 1 port4 10G Yes 2 3 base2 1G Yes 0-3 port2 40G Yes 0-3 fabric2 40G Yes 0-3 fabric4 40G Yes ------ ---- ------- ----- ----------

Hardware Acceleration

FortiGate-5001E and 5001E1 fast path architecture